DC Characteristics and Timing Specifications
Tables 5–50 and 5–51 show the LVDS timing budget for Cyclone II
devices. Cyclone II devices support LVDS receivers at data rates up to
805 Mbps, and LVDS transmitters at data rates up to 640 Mbps.
Table 5–50. LVDS Transmitter Timing Specification (Part 1 of 2)
–6 Speed Grade
–7 Speed Grade
–8 Speed Grade
Symbol Conditions
Unit
Max Max
Max Max
Max Max
Min
Typ
Min
Typ
Min
Typ
(1)
(2)
(1)
(2)
(1)
(2)
×10
×8
×7
×4
×2
×1
10
320
320
10
275
320
10
155.5
(4)
320
(6)
MHz
MHz
MHz
MHz
MHz
MHz
fHSCLK
(input
clock
fre-
quency)
—
—
—
10
10
10
10
10
320
320
320
320
320
320
320
320
10
10
10
10
10
275
275
275
275
320
320
320
320
10
10
10
10
10
155.5
(4)
320
(6)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
155.5
(4)
320
(6)
155.5
(4)
320
(6)
155.5
(4)
320
(6)
402.5 402.5
402.5 402.5
402.5 402.5
(8)
(8)
×10
×8
×7
×4
×2
×1
100
80
70
40
20
10
640
640
640
640
640
640
640
640
640
640
100
80
70
40
20
10
550
550
550
550
550
640
640
640
640
640
100
80
70
40
20
10
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
HSIODR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
311
550
(5)
(7)
311
550
(5)
(7)
311
550
(5)
(7)
311
550
(5)
(7)
311
550
(5)
(7)
402.5 402.5
402.5 402.5
402.5 402.5
(9)
55
—
(9)
45
—
—
55
—
45
—
—
55
—
45
—
—
%
ps
ps
tDUTY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
160
312.5
363.6
200
500
200
200
TCCS
(3)
500
250
ps
Output
jitter
(peak to
peak)
—
—
—
—
—
—
—
550 (10)
250 (11)
20–80%
150
200
250
150
200
150
200
ps
tRISE
Altera Corporation
February 2008
5–61
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
