DC Characteristics and Timing Specifications
Figure 5–5. RSDS Transmitter Clock to Data Relationship
Transmitter
Clock (5.88 ns)
Channel-to-Channel
Skew (1.68 ns)
Transmitter
Valid
Data
Transmitter
Valid
Data
At transmitter
tx_data[11..0]
At receiver
rx_data[11..0]
Valid
Data
Valid
Data
Total
Skew
t
(2 ns)
SU
t
(2 ns)
H
Table 5–49 shows the mini-LVDS transmitter timing budget for Cyclone II
devices at 311 Mbps. Cyclone II devices cannot receive mini-LVDS data
because the devices are intended for applications where they will be
driving display drivers. A maximum mini-LVDS data rate of 311 Mbps is
supported for Cyclone II devices using DDIO registers. Cyclone II
devices support mini-LVDS only in the commercial temperature range.
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 1 of 2)
–6 Speed Grade
–7 Speed Grade
–8 Speed Grade
Symbol
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK
(input
clock
×10
×8
×7
×4
×2
×1
10
10
10
10
10
10
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
311
10
10
10
10
10
10
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
311
10
10
10
10
10
10
—
—
—
—
—
—
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
frequency)
311
MHz
Altera Corporation
February 2008
5–59
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
