Timing Specifications
Table 5–48. RSDS Transmitter Timing Specification (Part 2 of 2)
–6 Speed Grade
–7 Speed Grade
–8 Speed Grade
Symbol
Conditions
Unit
Min Typ Max(1) Min Typ Max(1) Min Typ Max(1)
TCCS
—
—
—
—
—
—
200
500
—
—
—
—
200
500
—
—
—
—
200
500
ps
ps
Output
jitter (peak
to peak)
tRISE
tFALL
tLOCK
20–80%,
CLOAD = 5 pF
—
—
—
500
500
—
—
—
—
—
500
500
—
—
—
—
—
500
500
—
—
—
ps
ps
μs
80–20%,
CLOAD = 5 pF
—
100
100
100
Note to Table 5–48:
(1) These specifications are for a three-resistor RSDS implementation. For single-resistor RSDS in ×10 through ×2
modes, the maximum data rate is 170 Mbps and the corresponding maximum input clock frequency is 85 MHz.
For single-resistor RSDS in ×1 mode, the maximum data rate is 170 Mbps, and the maximum input clock frequency
is 170 MHz. For more information about the different RSDS implementations, refer to the High-Speed Differential
Interfaces in Cyclone II Devices chapter of the Cyclone II Device Handbook.
In order to determine the transmitter timing requirements, RSDS receiver
timing requirements on the other end of the link must be taken into
consideration. RSDS receiver timing parameters are typically defined as
tSU and tH requirements. Therefore, the transmitter timing parameter
specifications are tCO (minimum) and tCO (maximum). Refer to Figure 5–4
for the timing budget.
The AC timing requirements for RSDS are shown in Figure 5–5.
5–58
Altera Corporation
February 2008
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
