DC Characteristics and Timing Specifications
Table 5–51. LVDS Receiver Timing Specification
–6 Speed Grade
–7 Speed Grade
–8 Speed Grade
Symbol
Conditions
Unit
Min Typ
Max
Min Typ
Max
Min Typ
Max
fHSCLK
(input clock
frequency)
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
10
10
10
10
10
10
100
80
70
40
20
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
402.5
402.5
402.5
402.5
402.5
402.5
805
10
10
10
10
10
10
100
80
70
40
20
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
320
320
320
320
320
402.5
640
640
640
640
640
402.5
400
500
10
10
10
10
10
10
100
80
70
40
20
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
320 (1)
320 (1)
320 (1)
320 (1)
320 (1)
402.5 (3)
640 (2)
640 (2)
640 (2)
640 (2)
640 (2)
402.5 (4)
400
HSIODR
805
805
805
805
402.5
300
SW
Input jitter
tolerance
—
—
500
—
—
550
ps
tLOCK
—
—
—
100
—
—
100
—
—
ps
100 (5)
Notes to Table 5–51:
(1) For extended temperature devices, the maximum input clock frequency for x10 through x2 modes is 275 MHz.
(2) For extended temperature devices, the maximum data rate for x10 through x2 modes is 550 Mbps.
(3) For extended temperature devices, the maximum input clock frequency for x1 mode is 340 MHz.
(4) For extended temperature devices, the maximum data rate for x1 mode is 340 Mbps.
(5) For extended temperature devices, the maximum lock time is 500 us.
External Memory Interface Specifications
Table 5–52 shows the DQS bus clock skew adder specifications.
Table 5–52. DQS Bus Clock Skew Adder Specifications
Mode
DQS Clock Skew Adder
Unit
×9
155
190
ps
ps
×18
Note to Table 5–52:
(1) This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×9 DQ group is 155 ps or 77.5 ps.
Altera Corporation
February 2008
5–63
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
