Timing Specifications
Table 5–46. Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 4)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Dedicated Clock
Outputs
Column I/O Pins
–6 –7 –8
Row I/O Pins
–7
Drive
Strength
I/O Standard
–6
–8
–6
–7
–8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
DIFFERENTIAL_SSTL_
18_CLASS_II
16 mA
18 mA
8 mA
30
29
26
46
67
62
59
57
40
41
43
18
33
29
28
47
67
65
62
59
40
42
43
20
36
29
29
48
67
68
65
62
41
42
43
21
—
—
59
65
71
—
—
—
28
—
—
—
—
—
61
66
71
—
—
—
32
—
—
—
—
—
63
68
72
—
—
—
36
—
—
—
—
—
59
65
71
—
—
—
28
—
—
—
—
—
61
66
71
—
—
—
32
—
—
—
—
—
63
68
72
—
—
—
36
—
—
—
1.8V_
DIFFERENTIAL_HSTL_
CLASS_I
10 mA
12 mA
16 mA
18 mA
20 mA
8 mA
1.8V_
DIFFERENTIAL_HSTL_
CLASS_II
1.5V_
DIFFERENTIAL_HSTL_
CLASS_I
10 mA
12 mA
16 mA
1.5V_
DIFFERENTIAL_HSTL_
CLASS_II
LVDS
—
—
—
—
—
—
11
11
13
13
16
16
11
11
11
15
—
—
13
13
13
19
—
—
15
15
15
23
—
—
11
11
11
15
—
—
13
13
13
19
—
—
15
15
15
23
—
—
RSDS
MINI_LVDS
SIMPLE_RSDS
1.2V_HSTL
11
13
16
15
19
23
130
130
132
132
133
133
1.2V_
DIFFERENTIAL_HSTL
PCI
—
—
—
—
13
—
—
14
—
—
14
99
99
21
120
121
27
142
143
33
99
99
21
120
121
27
142
143
33
PCI-X
LVTTL
OCT_25
_OHMS
LVCMOS
2.5V
OCT_25
_OHMS
13
14
14
21
27
33
21
27
33
OCT_50
_OHMS
346
198
369
203
392
209
324
202
326
203
327
204
324
202
326
203
327
204
1.8V
OCT_50
_OHMS
5–54
Altera Corporation
February 2008
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
