欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP2C35F672C8N的Datasheet PDF文件第75页浏览型号EP2C35F672C8N的Datasheet PDF文件第76页浏览型号EP2C35F672C8N的Datasheet PDF文件第77页浏览型号EP2C35F672C8N的Datasheet PDF文件第78页浏览型号EP2C35F672C8N的Datasheet PDF文件第80页浏览型号EP2C35F672C8N的Datasheet PDF文件第81页浏览型号EP2C35F672C8N的Datasheet PDF文件第82页浏览型号EP2C35F672C8N的Datasheet PDF文件第83页  
Cyclone II Architecture
Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)
V
CCIO
Level
I/O Standard
Type
Input Output
Differential HSTL-15 class I
or class II
Pseudo
differential
(4)
(5)
1.5 V
(5)
1.8 V
2.5 V
(5)
3.3 V/
2.5 V/
1.8 V/
1.5 V
1.5 V
(5)
1.8 V
(5)
2.5 V
(5)
Top & Bottom
I/O Pins
Side I/O Pins
User I/O
Pins
CLK, User I/O CLK,
PLL_OUT
DQS
Pins
DQS
v
(7)
v
(6)
v
(6)
Differential HSTL-18 class I
or class II
Pseudo
differential
(4)
v
(7)
v
v
(6)
LVDS
RSDS and mini-LVDS
(8)
LVPECL
(9)
Differential
Differential
Differential
v
v
v
v
v
v
v
v
v
v
Notes to
Table 2–17:
(1)
(2)
(3)
(4)
To drive inputs higher than V
C C I O
Allow
LVTTL and LVCMOS input levels to overdrive input buffer
option in the Quartus II software.
These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.
PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.
Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.
This I/O standard is not supported on these I/O pins.
This I/O standard is only supported on the dedicated clock pins.
PLL_OUT
does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.
mini-LVDS and RSDS are only supported on output pins.
LVPECL is only supported on clock inputs.
(5)
(6)
(7)
(8)
(9)
f
For more information on Cyclone II supported I/O standards, see the
Selectable I/O Standards in Cyclone II Devices
chapter in Volume 1 of the
Cyclone II Device Handbook.
High-Speed Differential Interfaces
Cyclone II devices can transmit and receive data through LVDS signals at
a data rate of up to 640 Mbps and 805 Mbps, respectively. For the LVDS
transmitter and receiver, the Cyclone II device’s input and output pins
support serialization and deserialization through internal logic.
Altera Corporation
February 2007
2–53
Cyclone II Device Handbook, Volume 1