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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure & Features  
The reduced swing differential signaling (RSDS) and mini-LVDS  
standards are derivatives of the LVDS standard. The RSDS and  
mini-LVDS I/O standards are similar in electrical characteristics to  
LVDS, but have a smaller voltage swing and therefore provide increased  
power benefits and reduced electromagnetic interference (EMI).  
Cyclone II devices support the RSDS and mini-LVDS I/O standards at  
data rates up to 311 Mbps at the transmitter.  
A subset of pins in each I/O bank (on both rows and columns) support  
the high-speed I/O interface. The dual-purpose LVDS pins require an  
external-resistor network at the transmitter channels in addition to 100-Ω  
termination resistors on receiver channels. These pins do not contain  
dedicated serialization or deserialization circuitry. Therefore, internal  
logic performs serialization and deserialization functions.  
Cyclone II pin tables list the pins that support the high-speed I/O  
interface. The number of LVDS channels supported in each device family  
member is listed in Table 2–18.  
Table 2–18. Cyclone II Device LVDS Channels (Part 1 of 2)  
Number of LVDS  
Channels (1)  
Device  
Pin Count  
EP2C5  
EP2C8  
144  
208  
256  
144  
208  
256  
256  
484  
240  
256  
484  
484  
672  
484  
672  
31 (35)  
56 (60)  
61 (65)  
29 (33)  
53 (57)  
75 (79)  
EP2C15  
EP2C20  
52 (60)  
128 (136)  
45 (53)  
52 (60)  
128 (136)  
131 (139)  
201 (209)  
119 (127)  
189 (197)  
EP2C35  
EP2C50  
2–54  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007