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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC Characteristics and Timing Specifications  
Table 5–9. DC Characteristics for User I/O Pins Using Differential I/O Standards Note (1) (Part 2 of 2)  
V
OD (mV)  
ΔVOD (mV)  
VOCM (V)  
VOH (V)  
VOL (V)  
I/O Standard  
Min Typ Max Min Max Min  
Typ  
Max  
Min Max Min  
Max  
Differential 1.8-V  
HSTL class I  
and II (3)  
VCCIO  
– 0.4  
0.4  
Differential  
SSTL-2 class I  
(4)  
VTT  
+
VTT –  
0.57  
0.57  
Differential  
SSTL-2 class II  
(4)  
VTT  
+
VTT –  
0.76  
0.76  
Differential  
SSTL-18 class I  
(4)  
0.5 ×  
0.5 ×  
0.5 × VTT  
+
VTT –  
0.475  
VCCIO VCCIO VCCIO  
0.475  
+
0.125  
0.125  
Differential  
SSTL-18 class II  
(4)  
0.5 ×  
0.5 ×  
0.5 × VCCIO  
0.28  
VCCIO VCCIO VCCIO  
– 0.28  
+
0.125  
0.125  
Notes to Table 5–9:  
(1) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output  
pins.  
(2) The RSDS and mini-LVDS I/O standards are only supported on output pins.  
(3) The differential 1.8-V HSTL and differential 1.5-V HSTL I/O standards are only supported on clock input pins and  
PLL output clock pins.  
(4) The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock  
pins.  
Table 5–10 shows the types of pins that support bus hold circuitry.  
DC  
Characteristics  
for Different Pin  
Types  
Table 5–10. Bus Hold Support  
Pin Type  
Bus Hold  
I/O pins using single-ended I/O standards  
I/O pins using differential I/O standards  
Dedicated clock pins  
Yes  
No  
No  
No  
No  
JTAG  
Configuration pins  
Altera Corporation  
February 2008  
5–11  
Cyclone II Device Handbook, Volume 1