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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC Characteristics and Timing Specifications  
Table 5–7. DC Characteristics of User I/O Pins Using Single-Ended Standards Notes (1), (2) (Part 2 of 2)  
Test Conditions  
Voltage Thresholds  
I/O Standard  
I
OL (mA)  
IOH (mA)  
Maximum VOL (V)  
Minimum VOH (V)  
1.5-V HSTL class I  
1.5V HSTL class II  
8
–8  
0.4  
0.4  
VCCIO – 0.4  
VCCIO – 0.4  
16  
–16  
Notes to Table 5–7:  
(1) The values in this table are based on the conditions listed in Tables 5–2 and 5–6.  
(2) This specification is supported across all the programmable drive settings available as shown in the Cyclone II  
Architecture chapter of the Cyclone II Device Handbook.  
Differential I/O Standards  
The RSDS and mini-LVDS I/O standards are only supported on output  
pins. The LVDS I/O standard is supported on both receiver input pins  
and transmitter output pins.  
1
For more information on how these differential I/O standards  
are implemented, refer to the High-Speed Differential Interfaces in  
Cyclone II Devices chapter of the Cyclone II Device Handbook.  
Figure 5–1 shows the receiver input waveforms for all differential I/O  
standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II,  
differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and  
differential SSTL-18 class I and II).  
Altera Corporation  
February 2008  
5–7  
Cyclone II Device Handbook, Volume 1  
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