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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC Characteristics for Different Pin Types  
Table 5–11 specifies the bus hold parameters for general I/O pins.  
Table 5–11. Bus Hold Parameters  
Note (1)  
VCCIO Level  
2.5 V  
Parameter  
Conditions  
Unit  
1.8 V  
3.3 V  
Min  
Max  
Min  
Max  
Min  
Max  
Bus-hold low, sustaining  
current  
VIN  
>
30  
50  
70  
μA  
μA  
VIL(maximum)  
Bus-hold high, sustaining  
current  
VIN  
<
–30  
–50  
–70  
VIL(minimum)  
Bus-hold low, overdrive  
current  
0 V < VIN < VCCIO  
200  
–200  
1.07  
300  
–300  
1.7  
500  
–500  
2.0  
μA  
μA  
V
Bus-hold high, overdrive  
current  
0 V < VIN < VCCIO  
Bus-hold trip point (2)  
0.68  
0.7  
0.8  
Notes to Table 5–11:  
(1) There is no specification for bus-hold at VCCIO = 1.5 V for the HSTL I/O standard.  
(2) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.  
On-Chip Termination Specifications  
Table 5–12 defines the specifications for internal termination resistance  
tolerance when using series or differential on-chip termination.  
Table 5–12. Series On-Chip Termination Specifications  
Resistance Tolerance  
Extended/  
Symbol  
Description  
Conditions  
Commercial Industrial  
Automotive Unit  
Temp Max  
Max  
Max  
25-Ω RS  
50-Ω RS  
50-Ω RS  
Internal series termination without VCCIO = 3.3V  
calibration (25-Ω setting)  
30  
30  
40  
40  
50  
%
%
%
Internal series termination without VCCIO = 2.5V  
calibration (50-Ω setting)  
30  
30  
40  
Internal series termination without VCCIO = 1.8V  
calibration (50-Ω setting)  
30 (1)  
Note to Table 5–12:  
(1) For commercial –8 devices, the tolerance is 40%.  
5–12  
Altera Corporation  
February 2008  
Cyclone II Device Handbook, Volume 1