DDR Memory Interface Pins
Figure 9–13 shows waveforms of the circuit shown in Figure 9–11. The
first set of waveforms in Figure 9–13 shows the edge-aligned relationship
between the DQ and DQS signals at the Cyclone II device pins. The
second set of waveforms in Figure 9–13 shows what happens if the
shifted DQS signal is not inverted. In this case, the last data, Qn, does not
get latched into the logic array as DQS goes to tri-state after the read
postamble time. The third set of waveforms in Figure 9–13 shows a
proper read operation with the DQS signal inverted after the 90° shift.
The last data, Qn, does get latched. In this case the outputs of register AI
and register CI, which correspond to dataout_hand dataout_lports,
are now switched because of the DQS inversion. Register AI, register BI,
and register CI refer to the nomenclature in Figure 9–11.
Figure 9–13. DQ Captures With Noninverted & Inverted Shifted DQS
DQ & DQS Signals
DQ at the Pin
Q
Q
Q
n
n - 2
n - 1
DQS at the Pin
Shifted DQS Signal is Not Inverted
DQS Shifted by 90˚
Output of Register A (dataout_h)
I
Q
n - 1
Q
Q
Output of Register B
I
n - 2
n
Output of Register C (dataout_l)
I
Q
n - 2
Shifted DQS Signal is Inverted
DQS Inverted and
Shifted by 90˚
Output of Register A
I
Q
Q
Q
Q
n - 2
n
(dataout_h)
Output of Register B
Q
n - 1
I
I
Output of Register C
n - 3
n - 1
(dataout_I)
9–20
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
