External Memory Interfaces
Registers sync_reg_hand sync_reg_lsynchronize the two data
streams to the rising edge of the resynchronization clock. Figure 9–12
shows examples of functional waveforms from a double data rate input
implementation.
Figure 9–12. DDR Input Functional Waveforms
DQS
Delay_DQS
DQ
Q0
Q1
Q2
Q3
Output of
Input Register AI
Q1
Q3
Output of
Input Register BI
Q0
Q2
Output of
Register CI
Q0
Q2
resync_clk
dataout_h
dataout_l
Q1
Q0
Q3
Q2
The Cyclone II DDR input registers require you to invert the incoming
DQS signal to ensure proper data transfer. The altdqmegafunction
automatically adds the inverter on the clock port of the DQ signals. As
shown in Figure 9–11, the inverted DQS signal’s rising edge clocks
register AI, its falling edge clocks register BI, and register CIaligns the
data clocked by register BIwith register AIon the inverted DQS signal’s
rising edge. In a DDR memory read operation, the last data coincides with
the falling edge of DQS signal. If you do not invert the DQS pin, you do
not get this last data because the register does not latch until the next
rising edge of the DQS signal.
Altera Corporation
February 2007
9–19
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
