External Memory Interfaces
Figure 9–9. Cyclone II DQS Postamble Circuitry Connection
Capture Register
D
Q
ENA
Capture Register
Capture Register
DQ[7..0]
DQS
D
Q
D
Q
DQS'
ENA
ENA
Δt
Reset
DQS Programmable
Delay Chain
Circuitry
PRN
EnableN
Q
D
Postamble
Logic
CLRN
Global
Clock Network
Figure 9–10 shows the timing waveform for Figure 9–9. When the
postamble logic detects the falling DQS edge at the start of postamble, it
sends out a signal to disable the capture registers to prevent any
accidental latching.
Altera Corporation
February 2007
9–17
Cyclone II Device Handbook, Volume 1