Conclusion
Figure 9–17. DDR Bidirectional Waveforms
outclk
OE
datain h
datain_l
data1
data0
DQ
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DQS
Output of
Input Register A I
Q1
Q3
Output of
Input Register BI
Q0
Q2
Q2
Output of
Register CI
Q0
resync_clk
dataout_h
dataout_l
Q1
Q0
Q3
Q2
Cyclone II devices support SDR SDRAM, DDR SDRAM, DDR2 SDRAM,
and QDRII SRAM external memories. Cyclone II devices feature high-
speed interfaces that transfer data between external memory devices at
up to 167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and
167 MHz/667 Mbps for QDRII SRAM devices. The clock delay control
circuitry allows you to fine tune the phase shift for the input clocks or
strobes to properly align clock edges as needed to capture data.
Conclusion
9–24
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
