Board Layout
Figure 7–15. clkena Implementation
clkin
clkena
clkout
The clkenasignal can also disable clock outputs if the system is not
tolerant to frequency overshoot during PLL resynchronization.
Altera recommends using the clkenasignals when switching the clock
source to the PLLs or the global clock network. The recommended
sequence to be followed is:
1. Disable the primary output clock by de-asserting the clkenasignal.
2. Switch to the secondary clock using the dynamic select signals of the
clock control block.
3. Allow some clock cycles of the secondary clock to pass before
re-asserting the clkenasignal. The exact number of clock cycles
you need to wait before enabling the secondary clock is design
dependent. You can build custom logic to ensure glitch-free
transition when switching between different clock sources.
The PLL circuits in Cyclone II devices contain analog components
embedded in a digital device. These analog components have separate
power and ground pins to minimize noise generated by the digital
components.
Board Layout
7–30
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
