Clocking
From the clock sources listed above, only two clock input pins, two PLL
clock outputs, one DPCLKor CDPCLKpin, and one source from internal
logic can drive into any given clock control blocks, as shown in
Figure 7–11. Out of these six inputs to any clock control block, the two
clock input pins and two PLL outputs can be dynamic selected to feed a
global clock network. The clock control block supports static selection of
the DPCLKor CDPCLKpin and the signal from internal logic.
Figure 7–13 shows the simplified version of the four clock control blocks
on each side of the Cyclone II device periphery. The Cyclone II devices
support up to 16 of these clock control blocks and this allows for up to a
maximum of 16 global clocks in Cyclone II devices.
Figure 7–13. Clock Control Blocks on Each Side of the Cyclone II Device
4
Clock Input Pins
3
PLL Outputs
Clock
Control
Block
2
4
CDPCLK
GCLK
2 or 4 (1)
DPCLK
4
Internal Logic
Four Clock Control
Blocks on Each Side
of the Device
Note to Figure 7–13:
(1) The left and right sides of the device have two DPCLKpins, and the top and bottom
of the device have four DPCLKpins.
Global Clock Network Power Down
The Cyclone II global clock network can be disabled (powered down) by
both static and dynamic approaches. When a clock network is powered
down, all the logic fed by the clock network is in an off-state, thereby
reducing the overall power consumption of the device.
The global clock networks that are not used are automatically powered
down through configuration bit settings in the configuration file
generated by the Quartus II software.
The dynamic clock enable or disable feature allows internal logic to
synchronously control power up or down on the global clock networks in
the Cyclone II device. This function is independent of the PLL and is
applied directly on the clock network, as shown in Figure 7–11. The input
7–28
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
