Clocking
Figure 7–11. Clock Control Block
Clock Control Block
Internal Logic
DPCLK or
CDPCLK
Enable/
Disable
Global
Clock
Static Clock Select (3)
Static Clock
Select (3)
(3)
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
C0
C1
C2
inclk1
inclk0
f
IN
PLL
CLKSWITCH (1)
CLKSELECT[1..0] (2)
CLKENA (4)
Notes to Figure 7–11:
(1) The CLKSWITCHsignal can either be set through the configuration file or dynamically set when using the manual
PLL switchover feature. The output of the multiplexer is the input reference clock (fIN) for the PLL.
(2) The CLKSELECT[1..0]signals are fed by internal logic and can be used to dynamically select the clock source for
the global clock network when the device is in user mode.
(3) The static clock select signals are set in the configuration file and cannot be dynamically controlled when the device
is in user mode.
(4) Internal logic can be used to enable or disable the global clock network in user mode.
Each PLL generates three clock outputs through the c[1..0]and c2
counters. Two of these clocks can drive the global clock network through
the clock control block.
Global Clock Network Clock Source Generation
There are a total of 8 clock control blocks on the smaller Cyclone II devices
(EP2C5 and EP2C8 devices) and a total of 16 clock control blocks on the
larger Cyclone II devices (EP2C15 devices and larger). Figure 7–12 shows
the Cyclone II clock inputs and the clock control blocks placement.
7–26
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
