External Memory Interfaces
QDRII SRAM
QDRII SRAM is the second generation of QDR SRAM devices. QDRII
SRAM devices, which can transfer four words per clock cycle, fulfill the
requirements facing next-generation communications system designers.
QDRII SRAM devices provide concurrent reads and writes, zero latency,
increased data throughput, and allow simultaneous access to the same
address location.
Interface Pins
QDRII SRAM devices use two separate, unidirectional data ports for read
and write operations, enabling four times the data transfer compared to
single data rate devices. QDRII SRAM devices use common control and
address lines for read and write operations. Figure 9–3 shows the block
diagram for QDRII SRAM burst-of-two architecture.
Figure 9–3. QDRII SRAM Block Diagram for Burst-of-Two Architecture
Discrete QDRII SRAM Device
18
18
A
BWSn
WPSn
D
2
18
2
C, Cn (Optional)
RPSn
256K × 18
Memory
Array
256K × 18
Memory
Array
Write
Port
Read
Port
36
36
Q
Data
Data
CQ, CQn
2
K, Kn
VREF
Control
Logic
QDRII SRAM burst-of-two devices sample the read address on the rising
edge of the clock and the write address on the falling edge of the clock.
QDRII SRAM burst-of-four devices sample both read and write addresses
on the clock’s rising edge. Connect the memory device’s Q ports (read
data) to the Cyclone II DQ pins. You can use any of the Cyclone II device’s
user I/O pins in the top and bottom I/O banks for the D ports (write
data), commands, and addresses. For maximum performance, Altera
recommends connecting the D ports (write data) to the Cyclone II DQ
pins, because the DQ pins are pre-assigned to ensure minimal skew.
Altera Corporation
February 2007
9–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
