9. External Memory
Interfaces
CII51009-3.1
Improving data bandwidth is an important design consideration when
trying to enhance system performance without complicating board
design. Traditionally, doubling the data bandwidth of a system required
either doubling the system frequency or doubling the number of data I/O
pins. Both methods are undesirable because they complicate the overall
system design and increase the number of I/O pins. Using double data
rate (DDR) I/O pins to transmit and receive data doubles the data
bandwidth while keeping I/O counts low. The DDR architecture uses
both edges of a clock to transmit data, which facilitates data transmission
at twice the rate of a single data rate (SDR) architecture using the same
clock speed while maintaining the same number of I/O pins. DDR
transmission should be used where fast data transmission is required for
a broad range of applications such as networking, communications,
storage, and image processing.
Introduction
Cyclone® II devices support a broad range of external memory interfaces,
such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM.
Dedicated clock delay control circuitry allows Cyclone II devices to
interface with an external memory device at clock speeds up to
167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and
167 MHz/667 Mbps for QDRII SRAM devices. Although Cyclone II
devices also support SDR SDRAM, this chapter focuses on the
implementations of a double data rate I/O interface using the hardware
features available in Cyclone II devices and explains briefly how each
memory standard uses the Cyclone II features.
The easiest way to interface to external memory devices is by using one
of the Altera® external memory IP cores listed below.
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■
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DDR2 SDRAM Controller MegaCore® Function
DDR SDRAM Controller MegaCore Function
QDRII SRAM Controller MegaCore Function
OpenCore® Plus evaluations of these cores are available for free to
Quartus® II Web Edition software users. In addition, Altera software
subscription customers now receive full licenses to these MegaCore
functions as part of the IP-BASE suite.
Altera Corporation
February 2007
9–1
ALTERA [ ALTERA CORPORATION ]
