External Memory Interface Standards
Figure 9–5. Data & Clock Relationship During a QDRII SRAM Report
C/K
Cn/Kn
t
(2)
t
(2)
CO
CO
QA
QA + 1
QA + 2
QA + 3
Q
CQ
t
(3)
CLZ
t
(2)
t
(3)
DOH
CHZ
t
(4)
CQD
CQn
t
(5)
t
(4)
t
(4)
CQD
CCQO
CQOH
Notes to Figure 9–5:
(1) The timing parameter nomenclature is based on the Cypress QDRII SRAM data sheet for CY7C1313V18.
(2) tCO is the data clock-to-out time and tDOH is the data output hold time between burst.
(3) tCLZ and tC HZ are bus turn-on and turn-off times, respectively.
(4) tCQD is the skew between CQn and data edges.
(5) tCC QO and tC QOH are skew measurements between the C or C# clocks (or the K or K# clocks in single-clock mode)
and the CQ or CQn clocks.
When writing to QDRII SRAM devices, the write clock generates the data
while the K clock is 90° shifted from the write clock, creating a center-
aligned arrangement.
9–8
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
