External Memory Interfaces
Figure 9–4. CQ & CQn Connection for QDRII SRAM Read
dataout_h
DQ
LE
Register
LE
Register
sync_reg_l
Input Register AI
neg_reg_out
dataout_l
LE
Register
LE
Register
LE
Register
Dt
Dt
DQS/CQ# (CQn)
sync_reg_h
Register CI
Input Register BI
Clock Delay
Control Circuitry
resynch_clk
DQS/CQ (CQ)
Read & Write Operation
Figure 9–5 shows the data and clock relationships in QDRII SRAM
devices at the memory pins during reads. QDRII SRAM devices send data
within tCO time after each rising edge of the read clock C or C# in multi-
clock mode or the input clock K or K# in single clock mode. Data is valid
until tDOH time after each rising edge of the read clock C or C# in multi-
clock mode or the input clock K or K# in single clock mode. The CQ and
CQn clocks are edge-aligned with the read data signal. These clocks
accompany the read data for data capture in Cyclone II devices.
Altera Corporation
February 2007
9–7
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
