Memory Modes
outputs, respectively. When the output registers are bypassed, the new
data is available on the rising edge of the same clock cycle on which it was
written. See “Read-During- Write Operation at the Same Address” on
page 8–28 for waveforms and information on mixed-port
read-during-write mode.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location.
f
For the maximum synchronous write cycle time, refer to the Cyclone II
Device Family Data Sheet in volume 1 of the Cyclone II Device Handbook.
Figure 8–11 shows true dual-port timing waveforms for the write
operation at port A and the read operation at port B.
Figure 8–11. Cyclone II True Dual-Port Timing Waveforms
clk_a
wren_a
an
a0
a1
a2
a3
a4
a5
an-1
address_a
a6
data_a (1)
din-1
din
din4
din5
din6
din-2
din-1
din-1
din
din
dout0
dout0
dout1
dout1
dout2
dout2
dout3
dout3
din4
q_a (synch)
din4
din5
q_a (asynch)
clk_b
wren_b
address_b
q_b (synch)
bn
doutn-2
b1
b2
b3
b0
doutn-1
dout0
dout1
doutn
q_b (asynch)
dout0
dout2
doutn-1
doutn
dout1
Note to Figure 8–11:
(1) The crosses in the data_awaveform during write indicate “don’t care.”
Shift Register Mode
Cyclone II memory blocks can implement shift registers for digital signal
processing (DSP) applications, such as finite impulse response (FIR)
filters, pseudo-random number generators, multi-channel filtering, and
auto-correlation and cross-correlation functions. These and other DSP
8–14
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
