Cyclone II Memory Blocks
Figure 8–8. Cyclone II Simple Dual-Port Mode
Note (1)
Simple Dual-Port Memory
data[]
rdaddress[]
rden
wraddress[]
wren
q[]
byteena[]
rd_addressstall
wr_addressstall
wrclock
rdclock
rdclocken
rd_aclr
wrclocken
Note to Figure 8–8:
(1) Simple dual-port RAM supports input and output clock mode in addition to the
read and write clock mode shown.
Cyclone II memory blocks support mixed-width configurations, allowing
different read and write port widths. Tables 8–5 and 8–6 show the
mixed-width configurations.
Table 8–5. Cyclone II Memory Block Mixed-Width Configurations (Simple Dual-Port Mode)
Write Port
Read Port
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2K × 2
1K × 4
512 × 8
256 × 16
128 × 32
512 × 9
256 × 18
128 × 36
v
v
v
v
v
v
v
v
v
In simple dual-port mode, the memory blocks have one write enable and
one read enable signal. They do not support a clear port on the write
enable and read enable registers. When the read enable is deactivated, the
current data is retained at the output ports. If the read enable is activated
during a write operation with the same address location selected, the
simple dual-port RAM output is the old data stored at the memory
Altera Corporation
February 2008
8–11
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
