Memory Modes
Figure 8–4. Cyclone II Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
rden
a0
a1
a2
a3
a4
a5
a6
addressstall
latched address
(inside memory)
a5
a1
a4
an
a0
q (synch)
dout0
dout1
dout4
doutn-1
doutn
doutn
dout1
dout1
dout1
dout1
dout0
dout4
dout1
q (asynch)
dout5
Figure 8–5. Cyclone II Address Clock Enable During Write Cycle Waveform
inclock
a0
00
a1
01
a2
02
a3
03
a4
04
a5
05
a6
06
wraddress
data
wren
addressstall
latched address
(inside memory)
a1
a4
03
a5
an
XX
a0
00
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
01
02
XX
XX
04
XX
XX
05
Cyclone II M4K memory blocks include input registers that synchronize
writes and output registers to pipeline data, thereby improving system
performance. All M4K memory blocks are fully synchronous, meaning
that you must send all inputs through a register, but you can either send
outputs through a register (pipelined) or bypass the register
(flow-through).
Memory Modes
8–8
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2008
ALTERA [ ALTERA CORPORATION ]
