Cyclone II Memory Blocks
case writing is controlled only by the write enable signals. There is no
clear port to the byte enable registers. M4K blocks support byte enables
when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits.
When using data widths of 1, 2, 4, 8, and 9 bits, the byte enable behaves
as a redundant write enable because the data width is less than or equal
to a single byte. Table 8–3 summarizes the byte selection.
Table 8–3. Byte Enable for Cyclone II M4K Blocks Note (1)
Affected Bytes
byteena[3..0]
datain
datain
datain
datain
datain
datain
datain
datain
datain
× 1
× 2
× 4
× 8
× 9
× 16
× 18
× 32
× 36
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[0]
-
[1..0]
[3..0]
[7..0]
[8..0]
[7..0]
[8..0]
[7..0]
[8..0]
-
-
-
-
-
-
-
-
-
-
-
-
[15..8]
[17..9]
[15..8]
[17..9]
-
-
-
-
-
[23..16] [26..18]
[31..24] [35..27]
-
Note to Table 8–3:
(1) Any combination of byte enables is possible.
Table 8–4 shows the byte enable port control for true dual-port mode.
Table 8–4. Byte Enable Port Control for True Dual-Port Mode
byteena [3:0]
Affected Port
[1:0]
[3:2]
Port A (1)
Port B (1)
Note to Table 8–4:
(1) For any data width up to ×18 for each port.
Figure 8–2 shows how the wrenand byteenasignals control the
operations of the RAM.
When a byte enable bit is de-asserted during a write cycle, the
corresponding data byte output appears as a “don’t care” or unknown
value. When a byte enable bit is asserted during a write cycle, the
corresponding data byte output is the newly written data.
Altera Corporation
February 2008
8–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
