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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Transceivers  
Figure 2–19. Before & After the Channel Aligner  
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Rate Matcher  
The rate matcher, which is available only in XAUI and GIGE modes,  
consists of a 12-word deep FIFO buffer and a FIFO controller. The rate  
matcher is bypassed when the device is not in XAUI or GIGE mode.  
In a multi-crystal environment, the rate matcher compensates for up to a  
100-ppm difference between the source and receiver clocks.  
GIGE Mode  
In the GIGE mode, the rate matcher adheres to the specifications in  
clause 36 of the IEEE 802.3 documentation, for idle additions or removals.  
The rate matcher performs clock compensation only on /I2/ordered  
sets, composing a /K28.5/+followed by a /D16.2/-. The rate matcher  
does not perform a clock compensation on any other ordered set  
combinations. An /I2/ is added or deleted automatically based on the  
number of words in the FIFO buffer. A 9’h19Cis given at the control and  
data ports when the FIFO is in an overflow or underflow condition.  
Altera Corporation  
June 2006  
2–23  
Stratix GX Device Handbook, Volume 1  
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