PLLs & Clock Networks
Enhanced PLLs
Stratix GX devices contain up to four enhanced PLLs with advanced
clock management features. Figure 4–51 shows a diagram of the
enhanced PLL.
Figure 4–51. Stratix GX Enhanced PLL
Programmable
Time Delay on
Each PLL Port
Post-Scale
Counters
VCO Phase Selection
Selectable at Each
PLL Output Port
From Adjacent PLL
/l0
/l1
Δt
Δt
Regional
Clocks
Clock
Switch-Over
Circuitry
Spread
Spectrum
Phase Frequency
Detector
CLK0
CLK1
4
8
/n
Δt
Charge
Pump
Loop
Filter
Global
Clocks
Δt
/g0
PFD
VCO
/g1
/g2
Δt
Δt
Δt
/m
(1)
I/O Buffers
(2)
/g3
Δt
Δt
to I/O or general
routing
Lock Detect
& Filter
FBIN
/e0
/e1
VCO Phase Selection
Affecting All Outputs
Δt
Δt
4
/e2
/e3
Δt
I/O Buffers (3)
Notes to Figure 4–51:
(1) External feedback is available in PLLs 5 and 6.
(2) This external output is available from the g0 counter for PLLs 11 and 12.
(3) These counters and external outputs are available in PLLs 5 and 6.
4–82
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
