Stratix GX Architecture
Figure 4–50. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs Note (1)
(1)
PLL5_OUT[3..0] CLK14
(2)
CLK12
(1)
PLL5_FB
CLK15
(2)
CLK13
E[0..3]
PLL 5
PLL 11 (4)
L0 L1 G0 G1 G2 G3
G0 G1 G2 G3 L0 L1
PLL11_OUT
RCLK10
RCLK11
Regional
Clocks
RCLK2
RCLK3
G12
G13
G14
G15
Global
Clocks
G4
G5
G6
G7
RCLK6
RCLK7
Regional
Clocks
RCLK12
RCLK13
PLL12_OUT
L0 L1 G0 G1 G2 G3
PLL 6
G0 G1 G2 G3 L0 L1
PLL 12 (4)
PLL6_OUT[3..0]
PLL6_FB
(1)
CLK6 (1)
CLK7 (2)
CLK4
CLK5
(2)
Note to Figure 4–50:
(1) PLLs 5, 6, 11, and 12 are enhanced PLLs.
Altera Corporation
February 2005
4–81
Stratix GX Device Handbook, Volume 1