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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
Figure 4–50. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs Note (1)  
(1)  
PLL5_OUT[3..0] CLK14  
(2)  
CLK12  
(1)  
PLL5_FB  
CLK15  
(2)  
CLK13  
E[0..3]  
PLL 5  
PLL 11 (4)  
L0 L1 G0 G1 G2 G3  
G0 G1 G2 G3 L0 L1  
PLL11_OUT  
RCLK10  
RCLK11  
Regional  
Clocks  
RCLK2  
RCLK3  
G12  
G13  
G14  
G15  
Global  
Clocks  
G4  
G5  
G6  
G7  
RCLK6  
RCLK7  
Regional  
Clocks  
RCLK12  
RCLK13  
PLL12_OUT  
L0 L1 G0 G1 G2 G3  
PLL 6  
G0 G1 G2 G3 L0 L1  
PLL 12 (4)  
PLL6_OUT[3..0]  
PLL6_FB  
(1)  
CLK6 (1)  
CLK7 (2)  
CLK4  
CLK5  
(2)  
Note to Figure 4–50:  
(1) PLLs 5, 6, 11, and 12 are enhanced PLLs.  
Altera Corporation  
February 2005  
4–81  
Stratix GX Device Handbook, Volume 1  
 
 
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