Digital Signal Processing Block
Figure 4–38. Four-Multipliers Adder Mode
signa (1)
signb (1)
aclr
clock
ena
shiftin A
shiftin B
D
Q
Data A
ENA
D
Q
ENA
CLRN
Adder/Subtractor
CLRN
D
Q
Data B
ENA
CLRN
D
Q
Data A
Data Out
D
Q
ENA
D
Q
ENA
addnsub1 (2)
signa (2)
signb (2)
ENA
CLRN
Summation
CLRN
CLRN
addnsub3 (2)
D
Q
Data B
ENA
CLRN
D
Q
Data A
ENA
D
Q
ENA
CLRN
Adder/Subtractor
CLRN
D
Q
Data B
ENA
CLRN
D
Q
Data A
ENA
D
Q
ENA
CLRN
CLRN
D
Q
Data B
ENA
CLRN
shiftout B shiftout A
Notes to Figure 4–38:
(1) These signals are not registered or registered once to match the data path pipeline.
(2) These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
4–64
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
