Digital Signal Processing Block
Multiply-Accumulator Mode
In multiply-accumulator mode (see Figure 4–36), the DSP block drives
multiplied results to the adder/subtractor/accumulator block configured
as an accumulator. You can implement one or two multiply-accumulators
up to 18 × 18 bits in one DSP block. The first and third multiplier sub-
blocks are unused in this mode, since only one multiplier can feed one of
two accumulators. The multiply-accumulator output can be up to 52
bits—a maximum of a 36-bit result with 16 bits of accumulation. The
accum_sloadand overflowsignals are only available in this mode.
The addnsubsignal can set the accumulator for decimation and the
overflowsignal indicates underflow condition.
Figure 4–36. Multiply-Accumulate Mode
signa (1)
signb (1)
aclr
clock
ena
Shiftin A
Shiftin B
D
Q
Data A
Data B
Data Out
overflow
D
Q
ENA
D
Q
ENA
Accumulator
ENA
CLRN
CLRN
CLRN
D
Q
ENA
CLRN
addnsub (2)
signa (2)
signb (2)
Shiftout B Shiftout A
accum_sload (2)
Notes to Figure 4–36:
(1) These signals are not registered or registered once to match the data path pipeline.
(2) These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator
block to add or subtract the outputs of the multiplier block, which is
useful for applications such as FFT functions and complex FIR filters. A
single DSP block can implement two sums or differences from two
18 × 18-bit multipliers each or four sums or differences from two 9 × 9-bit
multipliers each.
4–62
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
