Digital Signal Processing Block
Figure 4–34. Simple Multiplier Mode
signa (1)
signb (1)
aclr
clock
ena
shiftin A
shiftin B
D
Q
Data A
Data B
Data Out
D
Q
ENA
D
Q
ENA
ENA
CLRN
CLRN
CLRN
D
Q
ENA
CLRN
shiftout B shiftout A
Note to Figure 4–34:
(1) These signals are not registered or registered once to match the data path pipeline.
DSP blocks can also implement one 36 × 36-bit multiplier in multiplier
mode. DSP blocks use four 18 × 18-bit multipliers combined with
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use the register
that is normally a multiplier-result-output register as a pipeline stage for
the 36 × 36-bit multiplier. Figure 4–35 shows the 36 × 36-bit multiply
mode.
4–60
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005
ALTERA [ ALTERA CORPORATION ]
