欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第128页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第129页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第130页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第131页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第133页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第134页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第135页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第136页  
Digital Signal Processing Block  
The DSP block is divided into eight block units that interface with eight  
LAB rows on the left and right. Each block unit can be considered half of  
an 18 × 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local  
interconnect region is associated with each DSP block. Like an LAB, this  
interconnect region can be fed with 10 direct link interconnects from the  
LAB to the left or right of the DSP block in the same row. All row and  
column routing resources can access the DSP block’s local interconnect  
region. The outputs also work similarly to LAB outputs as well. Nine  
outputs from the DSP block can drive to the left LAB through direct link  
interconnects and nine can drive to the right LAB though direct link  
interconnects. All 18 outputs can drive to all types of row and column  
routing. Outputs can drive right- or left-column routing. Figures 4–39  
and 4–40 show the DSP block interfaces to LAB rows.  
Figure 4–39. DSP Block Interconnect Interface  
DSP Block  
OA[17..0]  
MultiTrack  
MultiTrack  
Interconnect  
Interconnect  
A1[17..0]  
OB[17..0]  
B1[17..0]  
OC[17..0]  
A2[17..0]  
OD[17..0]  
B2[17..0]  
OE[17..0]  
A3[17..0]  
OF[17..0]  
B3[17..0]  
OG[17..0]  
A4[17..0]  
OH[17..0]  
B4[17..0]  
4–66  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
February 2005  
 
 复制成功!