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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
Figure 4–33. Adder/Output Blocks  
Note (1)  
Accumulator Feedback  
accum_sload0 (2)  
Result A  
overflow0  
Adder/  
Subtractor/  
addnsub1 (2)  
Accumulator1  
Output Selection  
Multiplexer  
Result B  
signa (2)  
Summation  
Output  
Register Block  
signb (2)  
Result C  
Adder/  
Subtractor/  
Accumulator2  
addnsub3 (2)  
overflow1  
Result D  
accum_sload1 (2)  
Accumulator Feedback  
Notes to Figure 4–33:  
(1) Adder/output block shown in Figure 4–33 is in 18 × 18-bit mode. In 9 × 9-bit mode, there are four adder/subtractor  
blocks and two summation blocks.  
(2) These signals are either not registered, registered once, or registered twice to match the data path pipeline.  
Altera Corporation  
February 2005  
4–57  
Stratix GX Device Handbook, Volume 1  
 
 
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