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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC & Switching Characteristics  
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 3)  
Symbol  
Parameter  
Min Typ  
Max  
Unit  
tFCOMP  
External feedback clock compensation  
6
ns  
time (3)  
fOUT  
Output frequency for internal global or  
regional clock  
0.3  
420  
MHz  
fOUT_EXT  
tOUTDUTY  
Output frequency for external clock (2)  
0.3  
45  
434  
55  
MHz  
%
Duty cycle for external clock output  
(when set to 50%)  
tJITTER  
Period jitter for external clock output (5)  
100 ps for >200 MHz outclk  
20 mUI for <200 MHz outclk  
ps or  
mUI  
tCONFIG5,6  
tCONFIG11,12  
Time required to reconfigure the scan  
chains for PLLs 5 and 6  
289/fSCANCLK  
Time required to reconfigure the scan  
chains for PLLs 11 and 12  
193/fSCANCLK  
tSCANCLK  
tDLOCK  
scanclk frequency (4)  
22  
MHz  
Time required to lock dynamically (after (8)  
switchover or reconfiguring any non-  
post-scale counters/delays) (6) (10)  
100  
μs  
tLOCK  
fVCO  
Time required to lock from end of  
device configuration (10)  
10  
400  
μs  
PLL internal VCO operating range  
300  
600 (7)  
MHz  
Altera Corporation  
August 2005  
6–65  
Stratix GX Device Handbook, Volume 1