High-Speed I/O Specification
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 3 of 3)
Symbol
Parameter
Min Typ
Max
Unit
tLSKEW
Clock skew between two external clock
outputs driven by the same counter
50
ps
tSKEW
Clock skew between two external clock
outputs driven by the different counters
with the same settings
75
ps
fSS
Spread spectrum modulation frequency 30
150
0.6
kHz
%
% spread
Percentage spread for spread
0.5
spectrum frequency (9)
tARESET
10
ns
Minimum pulse width on areset
signal
Notes to Tables 6–88 through 6–90:
(1) The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs.
(2) See “Maximum Input & Output Clock Rates” on page 6–54.
(3) tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
(4) This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
(5) Actual jitter performance may vary based on the system configuration.
(6) Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are
changed, then tDLOCK is equal to 0.
(7) The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected.
(8) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
(9) Exact, user-controllable value depends on the PLL settings.
(10) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
6–66
Altera Corporation
August 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
