DLL Jitter
Table 6–92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min
Max
55
Unit
%
tDUTY
Duty cycle for DFFIO 1× CLKOUT pin (3) 45
Period jitter for DIFFIO clock out (3)
tJITTER
80
ps
Period jitter for internal global or
regional clock
100 ps for >200 MHz outclk
20 mUI for <200 MHz outclk
ps or
mUI
tLOCK
m
Time required for PLL to acquire lock
10
1
100
32
μs
Multiplication factors for m counter (4)
Integer
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
counter (4), (5)
1
32
tARESET
10
ns
Minimum pulse width on areset
signal
Notes to Tables 6–91 & 6–92:
(1) See “Maximum Input & Output Clock Rates” on page 6–54.
(2) When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
(3) This parameter is for high-speed differential I/O mode only.
(4) These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
(5) High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
Table 6–93 reports the jitter for the DLL in the DQS phase-shift reference
circuit.
DLL Jitter
Table 6–93. DLL Jitter for DQS Phase Shift Reference Circuit
Frequency (MHz)
DLL Jitter (ps)
197 to 200
160 to 196
100 to 159
100
300
500
6–68
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005
ALTERA [ ALTERA CORPORATION ]
