Timing Model
Table 6–83. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 2 of 2)
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
1.8 V
422
422
422
300
300
400
400
400
400
400
400
400
400
400
400
422
422
422
422
422
300
400
645
645
300
645
422
422
422
250
250
350
350
350
350
350
350
350
350
350
350
422
422
422
422
422
250
350
645
645
275
645
390
390
390
200
200
300
300
300
300
300
300
300
300
300
300
390
390
390
390
390
200
300
640
640
275
640
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
Tables 6–84 and 6–85 show the maximum output clock rate for column
and row pins in Stratix GX devices.
Table 6–84. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 1 of 2)
I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
LVTTL
2.5 V
350
350
300
300
250
300
MHz
MHz
6–56
Altera Corporation
August 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
