Timing Model
Table 6–79. Stratix GX IOE Programmable Delays on Row Pins
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to
internal cells
Off
3,970
3,390
2,810
164
164
3,900
0
4,367
3,729
3,091
173
173
4,290
0
5,022
4,288
3,554
198
198
4,933
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
On
Small
Medium
Large
Off
Decrease input delay to
input register
On
Decrease input delay to
output register
Off
1,240
0
1,364
0
1,568
0
On
Increase delay to output
pin
Off
0
0
0
On
377
0
397
0
456
0
Increase delay to output
enable pin
Off
On
348
0
383
0
441
0
Increase output clock
enable delay
Off
On
180
260
260
0
198
286
286
0
227
328
328
0
Small
Large
Increaseinputclockenable Off
delay
On
Small
180
260
260
0
198
286
286
0
227
328
328
0
Large
Off
Increase output enable
clock enable delay
On
540
1,016
1,016
594
1,118
1,118
683
1,285
1,285
Small
Large
6–52
Altera Corporation
August 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
