DC & Switching Characteristics
Table 6–86. High-Speed Timing Specifications & Definitions (Part 2 of 2)
High-Speed Timing Specification Definitions
tFALL
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR
Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = tSW (max) – tSW (min).
Input jitter (peak-to-peak)
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Output jitter (peak-to-peak)
tDUTY
tLOCK
Table 6–87 shows the high-speed I/O timing specifications for Stratix GX
devices.
Table 6–87. High-Speed I/O Specifications (Part 1 of 4)
Notes (1), (2)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK (Clock
frequency)
(LVDS,
LVPECL,
HyperTransport
technology)
10
717
10
717
10
624 MHz
W = 1 to 30 for ≤ 717
Mbps
W = 2 to 30 for > 717
Mbps
fHSCLK
=
fHSDR / W
fHSCLK_DPA
74
717
74
717
74
717 MHz
Altera Corporation
August 2005
6–59
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
