Timing Model
Maximum Input & Output Clock Rates
Tables 6–81 through 6–83 show the maximum input clock rate for column
and row pins in Stratix GX devices.
Table 6–81. Stratix GX Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins
I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
LVTTL
2.5 V
422
422
422
422
422
300
300
400
400
400
400
400
400
400
400
400
400
422
422
422
422
422
300
400
645
645
300
500
422
422
422
422
422
250
250
350
350
350
350
350
350
350
350
350
350
422
422
422
422
422
250
350
645
645
275
500
390
390
390
390
390
200
200
300
300
300
300
300
300
300
300
300
300
390
390
390
390
390
200
300
622
622
275
450
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
6–54
Altera Corporation
August 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
