Timing Model
Table 6–75. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Standard
Unit
Min
Max
Min
Max
Min
Max
2.5-V LVTTL
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
830
250
140
100
1,510
420
350
1,740
1,160
690
50
872
263
147
105
1,586
441
368
1,827
1,218
725
53
1,002
302
169
120
1,824
507
423
2,101
1,400
833
61
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1.8-V LVTTL
1.5-V LVTTL
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS (1)
90
95
109
–60
120
24
–50
100
20
–52
105
21
–20
40
–21
42
–24
48
LVPECL (1)
PCML (1)
–60
70
–63
74
–73
85
HyperTransport Technology (1)
Table 6–76. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
4 mA
1,911
1,911
1,691
1,471
1,341
2,011
2,011
1,780
1,549
1,412
2,312
2,312
2,046
1,780
1,623
ps
ps
ps
ps
ps
8 mA
12 mA
24 mA
6–48
Altera Corporation
August 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
