I/O Structure
■
■
■
■
■
■
■
■
■
■
■
■
■
LVDS
LVPECL
3.3-V PCML
HyperTransport
Differential HSTL (on input/output clocks only)
Differential SSTL (on output column clock pins only)
GTL/GTL+
1.5-V HSTL class I and II
1.8-V HSTL Class I and II
SSTL-3 class I and II
SSTL-2 class I and II
SSTL-18 class I and II
CTT
Table 4–27 describes the I/O standards supported by Stratix GX devices.
Table 4–27. Stratix GX Supported I/O Standards (Part 1 of 2)
Input Reference
Board
Termination
Voltage (VTT)
(V)
Output Supply
Voltage (VREF
)
Voltage (VCCIO
)
I/O Standard
Type
(V)
(V)
LVTTL
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.75
1.25
0.8
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
3.3
2.5
1.5
2.5
N/A
N/A
1.5
1.8
1.8
2.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.75
1.25
1.20
1.5
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVDS
LVPECL
Differential
3.3-V PCML
HyperTransport
Differential HSTL (1)
Differential SSTL (2)
GTL
Differential
Differential
Differential
Differential
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
GTL+
1.0
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-18 class I and II
SSTL-2 class I and II
0.75
0.9
0.75
0.9
0.90
1.25
0.90
1.25
4–114
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
