Stratix Architecture
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers. Figure 2–27 shows a
memory block in read/write clock mode.
Altera Corporation
July 2005
2–49
Stratix Device Handbook, Volume 1