TriMatrix Memory
Figure 2–26. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2)
8 LAB Row
Clocks
Memory Block
8
256 ´ 16
data[ ]
address[ ]
byteena[ ]
D
Q
Q
Q
Data In
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
ENA
Read Address
D
ENA
To MultiTrack
Interconnect
Data Out
D
Q
ENA
Byte Enable
D
ENA
wraddress[ ]
rden
Write Address
Read Enable
D
Q
Q
ENA
D
ENA
wren
outclken
Write
Pulse
Generator
Write Enable
D
ENA
Q
inclken
wrclock
rdclock
Notes to Figure 2–26:
(1) All registers shown except the rdenregister have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
2–48
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
