Stratix Architecture
■
■
■
■
■
1.8-V HSTL Class I and II
SSTL-3 Class I and II
SSTL-2 Class I and II
SSTL-18 Class I and II
CTT
Table 2–31 describes the I/O standards supported by Stratix devices.
Table 2–31. Stratix Supported I/O Standards
Board
Termination
Voltage (VTT)
(V)
Input Reference
Output Supply
Voltage (VREF
)
Voltage (VCCIO
)
I/O Standard
Type
(V)
(V)
LVTTL
Single-ended
Single-ended
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.75
1.25
0.8
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
3.3
2.5
1.5
2.5
N/A
N/A
1.5
1.8
1.8
2.5
3.3
3.3
3.3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.75
1.25
1.20
1.5
LVCMOS
2.5 V
Single-ended
1.8 V
Single-ended
1.5 V
Single-ended
3.3-V PCI
Single-ended
3.3-V PCI-X 1.0
LVDS
Single-ended
Differential
LVPECL
Differential
3.3-V PCML
HyperTransport
Differential HSTL (1)
Differential SSTL (2)
GTL
Differential
Differential
Differential
Differential
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
GTL+
1.0
1.5-V HSTL Class I and II
1.8-V HSTL Class I and II
SSTL-18 Class I and II
SSTL-2 Class I and II
SSTL-3 Class I and II
AGP (1× and 2° )
CTT
0.75
0.9
0.75
0.9
0.90
1.25
1.5
0.90
1.25
1.5
1.32
1.5
N/A
1.5
Notes to Table 2–31:
(1) This I/O standard is only available on input and output clock pins.
(2) This I/O standard is only available on output column clock pins.
Altera Corporation
July 2005
2–123
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
