ACEX 1K Programmable Logic Device Family Data Sheet
Figure 20. ACEX 1K JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 17 shows the timing parameters and values for ACEX 1K devices.
Table 17. ACEX 1K JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
tJCP
TCKclock period
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCKclock high time
tJCL
TCKclock low time
50
tJPSU
tJPH
JTAG port setup time
20
JTAG port hold time
45
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
35
35
35
44
Altera Corporation
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