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EP1K30TC144-3N 参数 Datasheet PDF下载

EP1K30TC144-3N图片预览
型号: EP1K30TC144-3N
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件LTE
文件页数/大小: 86 页 / 1204 K
品牌: ALTERA [ ALTERA CORPORATION ]
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ACEX 1K Programmable Logic Device Family Data Sheet  
All ACEX 1K devices provide JTAG BST circuitry that complies with the  
IEEE Std.  
IEEE Std. 1149.1-1990 specification. ACEX 1K devices can also be  
configured using the JTAG pins through the ByteBlasterMV or BitBlaster  
download cable, or via hardware that uses the JamTM Standard Test and  
Programming Language (STAPL), JEDEC standard JESD-71. JTAG  
boundary-scan testing can be performed before or after configuration, but  
not during configuration. ACEX 1K devices support the JTAG  
instructions shown in Table 14.  
1149.1 (JTAG)  
Boundary-Scan  
Support  
Table 14. ACEX 1K JTAG Instructions  
JTAG Instruction  
Description  
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during  
normal device operation and permits an initial data pattern to be output at the device  
pins.  
EXTEST  
BYPASS  
Allows the external circuitry and board-level interconnections to be tested by forcing a  
test pattern at the output pins and capturing test results at the input pins.  
Places the 1-bit bypass register between the TDIand TDOpins, allowing the BST data  
to pass synchronously through a selected device to adjacent devices during normal  
operation.  
USERCODE  
IDCODE  
Selects the user electronic signature (USERCODE) register and places it between the  
TDIand TDOpins, allowing the USERCODE to be serially shifted out of TDO.  
Selects the IDCODE register and places it between TDIand TDO, allowing the IDCODE  
to be serially shifted out of TDO.  
ICR Instructions  
These instructions are used when configuring an ACEX 1K device via JTAG ports using  
a MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or a Jam File (.jam) or  
Jam Byte-Code File (.jbc) via an embedded processor.  
The instruction register length of ACEX 1K devices is 10 bits. The  
USERCODE register length in ACEX 1K devices is 32 bits; 7 bits are  
determined by the user, and 25 bits are pre-determined. Tables 15 and 16  
show the boundary-scan register length and device IDCODE information  
for ACEX 1K devices.  
Table 15. ACEX 1K Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EP1K10  
EP1K30  
EP1K50  
EP1K100  
438  
690  
798  
1,050  
42  
Altera Corporation  
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