ACEX 1K Programmable Logic Device Family Data Sheet
Tables 11 and 12 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
Input fall time
Input duty cycle
5
5
ns
ns
tF
tINDUTY
fCLK1
40
25
60
180
%
Input clock frequency (ClockBoost clock
multiplication factor equals 1)
MHz
fCLK2
Input clock frequency (ClockBoost clock
multiplication factor equals 2)
16
90
MHz
PPM
ps
fCLKDEV
Input deviation from user specification in the
25,000
Altera software (1)
(2)
tINCLKSTB Input clock stability (measured between
100
adjacent clocks)
tLOCK
Time required for ClockLock or ClockBoost
10
µs
to acquire lock (3)
tJITTER
Jitter on ClockLock or ClockBoost-
tINCLKSTB <100
tINCLKSTB < 50
250 (4)
200 (4)
60
ps
ps
%
generated clock (4)
tOUTDUTY Duty cycle for ClockLock or ClockBoost-
40
50
generated clock
38
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