ACEX 1K Programmable Logic Device Family Data Sheet
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Table 10. ACEX 1K SameFrame Pin-Out Support
Device
256-Pin
FineLine
BGA
484-Pin
FineLine
BGA
EP1K10
(1)
(1)
v
v
v
v
v
v
EP1K30
EP1K50
EP1K100
Note:
(1) This option is supported with a 256-pin FineLine BGA package and SameFrame
migration.
To support high-speed designs, -1 and -2 speed grade ACEX 1K devices
offer ClockLock and ClockBoost circuitry containing a phase-locked loop
(PLL) that is used to increase design speed and reduce resource usage. The
ClockLock circuitry uses a synchronizing PLL that reduces the clock delay
and skew within a device. This reduction minimizes clock-to-output and
setup times while maintaining zero hold times. The ClockBoost circuitry,
which provides a clock multiplier, allows the designer to enhance device
area efficiency by sharing resources within the device. The ClockBoost
feature allows the designer to distribute a low-speed clock and multiply
that clock on-device. Combined, the ClockLock and ClockBoost features
provide significant improvements in system performance and
bandwidth.
ClockLock &
ClockBoost
Features
The ClockLock and ClockBoost features in ACEX 1K devices are enabled
through the Altera software. External devices are not required to use these
features. The output of the ClockLock and ClockBoost circuits is not
available at any of the device pins.
The ClockLock and ClockBoost circuitry lock onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
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Altera Corporation
ALTERA [ ALTERA CORPORATION ]
