ACEX 1K Programmable Logic Device Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7 lists the sources for each peripheral control signal and shows how
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. Table 7 also shows the rows that can drive
global signals.
Table 7. Peripheral Bus Sources for ACEX Devices
Peripheral Control Signal
EP1K10
EP1K30
EP1K50
EP1K100
OE0
OE1
OE2
OE3
OE4
OE5
Row A
Row A
Row B
Row B
Row C
Row C
Row A
Row A
Row B
Row B
Row C
Row C
Row A
Row B
Row C
Row D
Row E
Row F
Row A
Row B
Row C
Row D
Row E
Row F
Row A
Row B
Row D
Row F
Row H
Row J
Row A
Row C
Row E
Row G
Row I
Row A
Row C
Row E
Row L
Row I
Row K
Row F
Row D
Row B
Row H
Row J
Row G
CLKENA0/CLK0/GLOBAL0
CLKENA1/OE6/GLOBAL1
CLKENA2/CLR0
CLKENA3/OE7/GLOBAL2
CLKENA4/CLR1
CLKENA5/CLK1/GLOBAL3
Row J
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-high pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/ O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
32
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